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january 2011 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers fan3213 / fan3214 dual-4a, high-speed, low-side gate drivers features ? industry-standard pinouts ? 4.5 to 18v operating range ? 5a peak sink/source at v dd = 12v ? 4.3a sink / 2.8a source at v out = 6v ? ttl input thresholds ? two versions of dual independent drivers: - dual inverting (fan3213) - dual non-inverting (fan3214) ? internal resistors turn driver off if no inputs ? millerdrive? technology ? 12ns / 9ns typical rise/fall times with 2.2nf load ? typical propagation delay under 20ns matched within 1ns to the other channel ? double current capability by paralleling channels ? standard soic-8 package ? rated from ?40c to +125c ambient applications ? switch-mode power supplies ? high-efficiency mosfet switching ? synchronous rectifier circuits ? dc-to-dc converters ? motor control description the fan3213 and fan3214 dual 4a gate drivers are designed to drive n- channel enhancement-mode mosfets in low-side switching applications by providing high peak current pulses during the short switching intervals. they are both available with ttl input thresholds. internal circuitry provides an under- voltage lockout function by holding the output low until the supply voltage is within the operating range. in addition, the drivers f eature matched internal propagation delays between a and b channels for applications requiring dual gat e drives with critical timing, such as synchronous rectifiers. this also enables connecting two drivers in parallel to effectively double the current capability dr iving a single mosfet. the fan3213/14 drivers incorporate millerdrive? architecture for the final output stage. this bipolar- mosfet combination provi des high current during the miller plateau stage of the mo sfet turn-on / turn-off process to minimize switching loss, while providing rail- to-rail voltage swing and reverse current capability. the fan3213 offers two inverting drivers and the fan3214 offers two non-inverting drivers. both are offered in a standard 8-pin soic package. fan3213 fan3214 figure 1. pin configurations ordering information part number logic input threshold package packing method quantity per reel fan3213tmx dual inverting channels ttl soic-8 tape & reel 2,500 fan3214tmx dual non-inverting channels ttl soic-8 tape & reel 2,500
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 2 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers package outlines figure 2. soic-8 (top view) thermal characteristics (1) package ? jl (2) ? jt (3) ? ja (4) ? jb (5) ? jt (6) units 8-pin small outline integrated circuit (soic) 38 29 87 41 2.3 c/w notes: 1. estimates derived from thermal simulati on; actual values depend on the application. 2. theta_jl ( ? jl ): thermal resistance between the semi conductor junction and the bottom surfac e of all the leads (including any thermal pad) that are typically soldered to a pcb. 3. theta_jt ( ? jt ): thermal resistance between the se miconductor junction and the top surfac e of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. theta_ja ( ja ): thermal resistance between junction and ambient, dependent on the pcb design, heat sinking, and airflow. the value given is for natural convection with no heatsink, us ing a 2s2p board, as specifi ed in jedec standards jesd51-2, jesd51-5, and jesd51-7, as appropriate. 5. psi_jb ( ? jb ): thermal characterization parameter providing co rrelation between semiconductor junction temperature and an application circuit board reference point fo r the thermal environment defined in note 4. for the soic-8 package, the board reference is defined as the pc b copper adjacent to pin 6. 6. psi_jt ( ? jt ): thermal characterization parameter providing corre lation between the semiconducto r junction temperature and the center of the top of the package for the thermal environment defined in note 4.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 3 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers pin configurations fan3213 fan3214 figure 3. pin configurations (repeated) pin definitions pin name pin description 1 nc no connect. this pin can be grounded or left floating. 2 ina input to channel a . 3 gnd ground . common ground reference for input and output circuits. 2 ina input to channel a . 4 inb input to channel b . 7 outa gate drive output a : held low unless required input(s) are present and v dd is above uvlo threshold. 5 (fan3213) outb gate drive output b (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. 5 (fan3214) outb gate drive output b : held low unless required input(s) are present and v dd is above uvlo threshold. 6 vdd supply voltage . provides power to the ic. 7 (fan3213) outa gate drive output a (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. 7 (fan3214) outa gate drive output a : held low unless required input(s) are present and v dd is above uvlo threshold. 8 nc no connect. this pin can be grounded or left floating. output logic fan3213 (x=a or b) fan3214 (x=a or b) inx outx inx outx 0 0 0 (7) 0 1 (7) 0 1 0 0 1 0 (7) 0 1 (7) 0 1 1 note: 7. default input signal if no external connection is made.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 4 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers block diagrams figure 4. fan3213 block diagram figure 5. fan3214 block diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 5 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd vdd to pgnd -0.3 20.0 v v in ina, ina+, ina?, inb, inb+ and inb? to gnd gnd - 0.3 v dd + 0.3 v v out outa and outb to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature -55 +150 oc t stg storage temperature -65 +150 oc esd electrostatic discharge protection level human body model, jedec jesd22-a114 4 kv charged device model, jedec jesd22-c101 1 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v in input voltage ina, ina+, ina?, inb, inb+ and inb? 0 v dd v t a operating ambient te mperature -40 +125 oc
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 6 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers electrical characteristics unless otherwise noted, v dd =12v, t j =-40c to +125c. currents are defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4.5 18.0 v i dd supply current, inputs not connected 0.70 0.95 ma v on turn-on voltage ina = v dd , inb = 0v 3.5 3.9 4.3 v v off turn-off voltage ina = v dd , inb = 0v 3.3 3.7 4.1 v inputs v il_t inx logic low threshold 0.8 1.2 v v ih_t inx logic high threshold 1.6 2.0 v i in+ non-inverting input in from 0 to v dd -1.5 175.0 a i in- inverting input in from 0 to v dd -175.0 1.5 a v hys_t ttl logic hysteresis voltage 0.2 0.4 0.8 v output i sink out current, mid-voltage, sinking (8) outx at v dd /2, c load =0.22f, f=1khz 4.3 a i source out current, mid-voltage, sourcing (8) outx at v dd /2, c load =0.22f, f=1khz -2.8 a i pk_sink out current, peak, sinking (8) c load =0.22f, f=1khz 5 a i pk_source out current, peak, sourcing (8) c load =0.22f, f=1khz -5 a t rise output rise time (9) c load =2200pf 12 20 ns t fall output fall time (9) c load =2200pf 9 17 ns t d1 , t d2 output propagation delay, ttl inputs (9) 0 - 5v in , 1v/ns slew rate 9 17 29 ns propagation matching between channels ina=inb, outa and outb at 50% point 2 4 ns i rvs output reverse current withstand (8) 500 ma notes: 8. not tested in production. 9. see timing diagrams of figure 6 and figure 7. figure 6. non-inverting timing diagram figure 7. inverting timing diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 7 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 8. i dd (static) vs. supply voltage (10) figure 9. i dd (static) vs. temperature (10) figure 10. i dd (no load) vs. frequency figure 11. i dd (2.2nf load) vs. frequency figure 12. input thresholds vs. supply voltage figure 13. input thresholds vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 8 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. uvlo threshold vs. temperature figure 14. propagation delay vs. supply voltage figure 15. propagation delay vs. supply voltage figure 16. propagation delays vs. temperature figure 17. propagation delays vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 9 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 18. fall time vs. supply voltage figure 19. rise time vs. supply voltage figure 20. rise and fall times vs. temperature figure 21. rise/fall waveforms with 2.2nf load figure 22. rise/fall waveforms with 10nf load
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 10 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 23. quasi-static source current with v dd =12v (11) figure 24. quasi-static sink current with v dd =12v (11) figure 25. quasi-static source current with v dd =8v (11) figure 26. quasi-static sink current with v dd =8v (11) notes: 10. for any inverting inputs pulled low, non-inverting inputs pulled high , or outputs driven high; static i dd increases by the current flowing th rough the corresponding pull-up/down resist or shown in figure 4 and figure 5. 11. the initial spike in each current wa veform is a measurement artifact caused by the stray induct ance of the current- measurement loop. test circuit figure 27. quasi-static i out / v out test circuit
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 11 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers applications information input thresholds the fan3213 and the fan3214 drivers consist of two identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. the input thresholds meet industry-standard ttl-logic thresholds independent of the v dd voltage, and there is a hysteresis voltage of approx imately 0.4v. these levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges with a slew rate of 6v/s or faster, so a rise time from 0 to 3.3v should be 550ns or less. with reduced slew rate, circuit noise could cause the driver i nput voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. static supply current in the i dd (static) typical performance characteristics shown in figure 8 and figure 9, each curve is produced with both inputs floati ng and both outputs low to indicate the lowest static i dd current. for other states, additional current flows through the 100k ? resistors on the inputs and outputs shown in the block diagram of each part (see figure 4 and figure 5) . in these cases, the actual static i dd current is the value obtained from the curves plus this additional current. millerdrive? gate drive technology fan3213 and fan3214 gate driv ers incorporate the millerdrive? architecture shown in figure 28. for the output stage, a combination of bipolar and mos devices provide large currents ov er a wide range of supply voltage and temperature variat ions. the bipolar devices carry the bulk of the current as out swings between 1/3 to 2/3 v dd and the mos devices pu ll the output to the high or low rail. the purpose of the millerdrive ? architecture is to speed up switching by providing hi gh current during the miller plateau region when the gate- drain capacitance of the mosfet is being charged or discharged as part of the turn-on / turn-off process. for applications with zero voltage switching during the mosfet turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the miller plateau is not present. th is situation often occurs in synchronous rectifier app lications because the body diode is generally conducting before the mosfet is switched on. the output pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slower rise or fall time at the mosfet gate is needed. figure 28. millerdrive? output architecture under-voltage lockout the fan321x startup logic is optimized to drive ground- referenced n-channel mosfets with an under-voltage lockout (uvlo) function to ens ure that the ic starts up in an orderly fashion. when v dd is rising, yet below the 3.9v operational level, this circuit holds the output low, regardless of the status of the input pins. after the part is active, the supply voltage must drop 0.2v before the part shuts down. this hyster esis helps prevent chatter when low v dd supply voltages have noise from the power switching. this confi guration is not suitable for driving high-side p-channel mosfets because the low output voltage of t he driver would turn the p-channel mosfet on with v dd below 3.9v. v dd bypass capacitor guidelines to enable this ic to turn a device on quickly, a local high-frequency bypass capacitor, c byp , with low esr and esl should be connect ed between the vdd and gnd pins with minimal trace l ength. this capacitor is in addition to bulk electrolytic capacitance of 10f to 47f commonly found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd supply to 5%. this is often achieved with a value 20 times the equivalent load capacitance c eqv , defined here as q gate /v dd . ceramic capacitors of 0.1f to 1f or larger are common choices, as are dielectrics, such as x5r and x7r, with good temperatur e characteristics and high pulse current capability. if circuit noise affects normal operation, the value of c byp may be increased, to 50-100 times the c eqv , or c byp may be split into two c apacitors. one should be a larger value, based on equiva lent load capacitance, and the other a smaller value, such as 1-10nf mounted closest to the vdd and gnd pins to carry the higher- frequency components of the current pulses. the bypass capacitor must provi de the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the c byp would be twice as large as when a single channel is switching.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 12 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers layout and connection guidelines the fan3213 and fan3214 gate drivers incorporate fast-reacting input circuits , short propagation delays, and powerful output stages capabl e of delivering current peaks over 4a to facilitate voltage transition times from under 10ns to over 150ns. the following layout and connection guidelines are strongly recommended: ? keep high-current output and power ground paths separate from logic input signals and signal ground paths. this is especially critical for ttl-level logic thresholds at driver input pins. ? keep the driver as close to the load as possible to minimize the length of high-current traces. this reduces the series induc tance to improve high- speed switching, while r educing the loop area that can radiate emi to the driver inputs and surrounding circuitry. ? if the inputs to a channel are not externally connected, the internal 100k ? resistors indicated on block diagrams command a low output. in noisy environments, it may be necessary to tie inputs of an unused channel to vdd or gnd using short traces to prevent noise from causing spurious output switching. ? many high-speed power circuits can be susceptible to noise injected from t heir own output or other external sources, possibly causing output re- triggering. these effect s can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input or output leads. for best results, make connections to all pins as short and direct as possible. ? fan3213 and fan3214 are pin-compatible with many other industry-standard drivers. ? the turn-on and turn-off current paths should be minimized, as discussed in the following section. figure 29 shows the pulsed gate drive current path when the gate driver is suppl ying gate charge to turn the mosfet on. the current is supplied from the local bypass capacitor, c byp , and flows through the driver to the mosfet gate and to gr ound. to reach the high peak currents possible, the resistance and inductance in the path should be minimized. the localized c byp acts to contain the high peak current pulses within this driver- mosfet circuit, preventing them from disturbing the sensitive analog circuitry in the pwm controller. figure 29. current path for mosfet turn-on figure 30 shows the current path when the gate driver turns the mosfet off. idea lly, the driver shunts the current directly to the source of the mosfet in a small circuit loop. for fast turn -off times, the resistance and inductance in this path should be minimized. figure 30. current path for mosfet turn-off
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 13 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers operational waveforms at power-up, the driver output remains low until the v dd voltage reaches the turn-on threshold. the magnitude of the out pulses rises with v dd until steady- state v dd is reached. the non- inverting operation illustrated in figure 31 show s that the output remains low until the uvlo thres hold is reached, then the output is in-phase with the input. figure 31. non-inverting startup waveforms the inverting configuration of startup waveforms are shown in figure 32. with in+ tied to vdd and the input signal applied to in?, the out pulses are inverted with respect to the input. at pow er-up, the inverted output remains low until the v dd voltage reaches the turn-on threshold, then it follows t he input with inverted phase. figure 32. inverting startup waveforms
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 14 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers thermal guidelines gate drivers used to switch mosfets and igbts at high frequencies can dissipate significant amounts of power. it is important to determine the driver power dissipation and the resulting j unction temperature in the application to ensure that t he part is operating within acceptable temperature limits. the total power dissipation in a gate driver is the sum of two components, p gate and p dynamic : p total = p gate + p dynamic (1) gate driving loss: the most significant power loss results from supplying gat e current (charge per unit time) to switch the load mosfet on and off at the switching frequency. the power dissipation that results from driving a mo sfet at a specified gate- source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: p gate = q g ? v gs ? f sw ? n (2) where n is the number of driver channels in use (1 or 2). dynamic pre-drive / shoot-through current: a power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the graphs in typical performance characteristics to determine the current i dynamic drawn from v dd under actual operating conditions: p dynamic = i dynamic ? v dd ? n (3) once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the fo llowing thermal equation, assuming ? jb was determined for a similar thermal design (heat sinking and air flow): t j = p total ? ? jb + t b (4) where: t j = driver junction temperature; ? jb = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and t b = board temperature in location as defined in the thermal characteristics table. to give a numerical example, if the synchronous rectifier switches in the forward converter of figure 33 are fdms8660s, the datasheet give s a total gate charge of 60nc at v gs = 7v, so two devices in parallel would have 120nc gate charge. at a sw itching frequency of 300khz, the total power dissipation is: p gate = 120nc ? 7v ? 300khz ? 2 = 0.504w (5) p dynamic = 7.5ma ? 7v ? 2 = 0.011w (6) p total = 0.515w 0.52w (7) the soic-8 has a junction-to-board thermal characterization parameter of ? jb = 42c/w. in a system application, the localized te mperature around the device is a function of the layout and construction of the pcb along with airflow across the surfaces. to ensure reliable operation, the maximu m junction temperature of the device must be prev ented from exceeding the maximum rating of 150c; with 80% derating, t j would be limited to 120c. rearr anging equation 4 determines the board temperature required to maintain the junction temperature below 120c: t b,max = t j - p total ? ? jb (8) t b,max = 120c ? 0.52w ? 42c/w = 98c (9)
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 15 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers typical application diagrams figure 33. high-current forward converter with synchronous rectification figure 34. center-tapped bridge output with synchronous rectifiers pwm-a pwm-b pwm-c pwm-d secondary phase shift controller vin qa qb qc qd sr-2 sr-1 fan3214 fan3227 fan3227 figure 35. secondary controlled full bridge with current doubler output, synchronous rectifiers (simplified)
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 16 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers table 1. related products type part number gate drive (12) (sink/src) input threshold logic package single 1a fan3111c +1.1a / -0.9a cmos single channel of dual-input/single-output sot23-5, mlp6 single 1a fan3111e +1.1a / -0.9a external (13) single non-inverting channel with ex ternal reference sot23-5, mlp6 single 2a fan3100c +2.5a / -1.8a cmos single c hannel of two-input/one-output sot23-5, mlp6 single 2a fan3100t +2.5a / -1.8a ttl single c hannel of two-input/one-output sot23-5, mlp6 dual 2a fan3216t +2.5a / -1.8a ttl dual inverting channels soic8 dual 2a fan3217t +2.5a / -1.8a ttl dual non-inverting channels soic8 dual 2a fan3226c +2.4a / -1.6a cmos dual inverting channels + dual enable soic8, mlp8 dual 2a fan3226t +2.4a / -1.6a ttl dual in verting channels + dual enable soic8, mlp8 dual 2a fan3227c +2.4a / -1.6a cmos dual n on-inverting channels + dual enable soic8, mlp8 dual 2a fan3227t +2.4a / -1.6a ttl dual non- inverting channels + dual enable soic8, mlp8 dual 2a fan3228c +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.1 soic8, mlp8 dual 2a fan3228t +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.1 soic8, mlp8 dual 2a fan3229c +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.2 soic8, mlp8 dual 2a fan3229t +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.2 soic8, mlp8 dual 2a fan3268t +2.4a / -1.6a ttl 20v non-inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 dual 2a FAN3278T +2.4a / -1.6a ttl 30v non-inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 dual 4a fan3213t +2.5a / -1.8a ttl dual inverting channels soic8 dual 4a fan3214t +2.5a / -1.8a ttl dual non-inverting channels soic8 dual 4a fan3223c +4.3a / -2.8a cmos dual inverting channels + dual enable soic8, mlp8 dual 4a fan3223t +4.3a / -2.8a ttl dual in verting channels + dual enable soic8, mlp8 dual 4a fan3224c +4.3a / -2.8a cmos dual n on-inverting channels + dual enable soic8, mlp8 dual 4a fan3224t +4.3a / -2.8a ttl dual non- inverting channels + dual enable soic8, mlp8 dual 4a fan3225c +4.3a / -2.8a cmos dual channels of two-input/one-output soic8, mlp8 dual 4a fan3225t +4.3a / -2.8a ttl dual channels of two-input/one-output soic8, mlp8 single 9a fan3121c +9.7a / -7.1a cmos singl e inverting channel + enable soic8, mlp8 single 9a fan3121t +9.7a / -7.1a ttl singl e inverting channel + enable soic8, mlp8 single 9a fan3122t +9.7a / -7.1a cmos single non-inverting channel + enable soic8, mlp8 single 9a fan3122c +9.7a / -7.1a ttl single non-inverting channel + enable soic8, mlp8 notes: 12. typical currents with outx at 6v and v dd= 12v. 13. thresholds proportional to an exte rnally supplied reference voltage.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 17 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 36. 8-lead small outline integrated circuit (soic) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3213 / fan3214 ? rev. 1.0.2 18 fan3213 / fan3214 ? dual-4a, high-speed, low-side gate drivers

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